1. Field of the Invention
The present invention relates to a non-volatile memory device and fabricating method thereof, and more particularly, to an embedded non-volatile memory device having a high integration degree and fabricating method thereof.
2. Discussion of the Related Art
Lately, developments for non-volatile memory devices capable of keeping data despite power cut-off are rapidly in progress. As non-volatile memory devices, there are single poly type EEPROM, dual poly type EEPROM, stacked gate type flash memory device, split gate type flash memory device, SONOS flash memory device, and the like. In many applications of the non-volatile memory devices, the embedded non-volatile memory device combining logic and memory therein employs various kinds of non-volatile memory devices according to the integration requirements and the like.
FIG. 1 is a table for cell and chip sizes of various non-volatile memory devices. And, FIG. 2 is a table for the number of mask layers in 0.18 μm logic process for various non-volatile memory devices.
Referring to FIG. 1 and FIG. 2, if the degree of cell integration exceeds 100 K in case of the single poly type EEPROM having the simplest process, i.e., the smallest number of mask layers in the 0.18 μm logic process, the cell and chip sizes are too large to be efficient.
On the contrary, in case of the stacked gate type flash memory device, if the degree of cell integration becomes at least 1 M, the corresponding fabrication is very complicated despite its high degree of integration.
And, in case of the SONOS flash memory device, the cell size is relatively small at the low degree of integration and its fabrication is simple.
FIG. 3 is a layout of an embedded non-volatile memory device having the SONOS configuration according to a related art. And, FIG. 4 and FIG. 5 are cross-sectional diagrams of the memory device bisected along cutting lines IV-IV′ and V-V′, respectively.
Referring to FIGS. 3 to 5, an n-well 104 is formed in an upper part of a semiconductor substrate 102 and an active area is defined in an upper part of the n-well 104 of the semiconductor substrate 102 by a shallow trench isolating (STI) layer 101. And, a p-well 106 is arranged in the active area. Since the shallow trench isolation layer 101 is used, a bottom of the p-well 106 is lower than that of the trench isolation layer 101. And, an n+ source region 108, n+ drain region 110, and p+ contact region 120 are separately arranged in an upper part of the p-well 106.
A channel region lies between the n+ source region 108 and the n+ drain region 110. An ONO (lower oxide layer/nitride layer/upper oxide layer) layer 122 is arranged on the channel region. And, a conductor layer 124 as a wordline is arranged on the ONO layer 122. In the ONO layer 122, the lower oxide layer is a tunnel oxide layer, the nitride layer is a charge trap layer, and the upper oxide layer is an insulating layer.
The n+ drain region 110 is electrically connected to a first metal electrode 126 via a first contact plug 128. And, the p+ drain region 120 is electrically connected to a second metal electrode 130 via a second contact plug 132. Moreover, the n+ source region 108 is electrically connected to a third metal electrode (not shown in the drawing).
In the above-configured SONOS flash memory device, a length of a unit cell C1 is total 2.6 μm by adding a width 0.6 μm of the p-well 106 to a width 2.0 μm of the shallow trench isolating layer 101. And, a width of the unit cell C1 is 0.81 μm. Hence, an area of the unit cell C1 is 2.16 μm2.
However, even if the cell size, as shown in the table of FIG. 1, is relatively small in case of low integration degree, e.g., integration degree smaller than 10 M, the cell size increases in case of the cell integration degree above 10 M to weaken the competitiveness.